1. Field of the Invention
The present invention relates to a clock generating circuit and particularly, to a clock generating circuit that generates a clock signal when an activating signal is at a first level, while ceasing generation of a clock signal when the activating signal is at a second level.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) has been mainly fabricated in a CMOS process, wherein memory cells thereof are each constructed from an N channel MOS transistor and a capacitor. When data is written onto a memory cell, a boosted potential Vpp higher than a normal H level (external power source potential ExVdd) is applied to the gate of the N channel MOS transistor in order to prevent a potential drop in the N channel MOS transistor. For this reason, a boosted potential generating circuit for generating the boosted potential Vpp from the external power source potential ExVdd is incorporated in DRAM.
FIG. 11 is a circuit block diagram representing a main part of such a boosted potential generating circuit.
In FIG. 11, the boosted potential generating circuit includes: a clock generating circuit 50; and a charge pump circuit 51. The clock generating circuit 50, as shown in FIG. 12, includes: a NAND gate 55 and inverters 56 and 57. The inverters 56 and 57 are connected in series between the output node of the NAND gate 55 and one input node thereof. The other input node thereof receives an activating signal xcfx86EN. The activating signal xcfx86EN goes to H level when the boosted potential Vpp is lower than a target potential Vt, while the activating signal xcfx86EN goes to L level when the boosted potential Vpp is higher than the target potential Vt. An output signal of the NAND gate 55 serves as a clock signal CLK.
When the activating signal xcfx86EN is at H level, the NAND gate 55 acts as an inverter for an output signal of the inverter 57, and the NAND gate 55 and the inverters 56 and 57 constitutes a ring oscillator. Hence, a level of the clock signal CLK is inverted each time when a delay time of the NAND gate and the inverters 56 and 57 elapses. When the activating signal xcfx86EN goes to L level, an output level of the NAND gate 55 is fixed at H level.
Returning to FIG. 11, the charge pump circuit 51 includes: diodes 52 and 53; and a capacitor 54. The diodes 52 and 53 are connected in series between an external power source potential ExVdd line and an output node N53. One terminal of the capacitor 54 receives the clock signal CLK, while the other terminal thereof is connected to the cathode (node N52) of the diode 52.
FIG. 13 is a time chart representing operation of the boosted potential generating circuit shown in FIG. 11. It is assumed that in an initial state, the boosted potential Vpp is sufficiently lower than the target potential Vt, the activating signal xcfx86EN is forced to go to H level to activate the clock generating circuit 50, thus inverting a level of the clock signal CLK after each elapse of a prescribed time.
During a period in which the clock signal CLK is at L level (ground potential GND), a current flows into the capacitor 54 from the external power source potential ExVdd line through the diode 52, and the capacitor 54 is precharged to ExVddxe2x88x92Vd, wherein Vd indicates threshold voltages of the respective diodes 52 and 53.
When the clock signal CLK is raised to H level (ExVdd) following the precharge, a level of the node N52 is boosted to 2ExVddxe2x88x92Vd through the capacitor 54 and a positive electric charge is supplied to the output node N53 from the node N52. A level of the node N52 comes to be Vpp+Vd.
That is, when the activating signal xcfx86EN is at H level, the capacitor 54 is charged during a period in which the clock signal CLK (precharge period) is at L level, while a charge of the capacitor 50 is supplied to the output node N53 during a period in which the clock CLK is at H level (pump period) to boost a potential of the output node N53.
When the boosted potential Vpp reaches the target potential Vt and the activating signal xcfx86EN goes to L level, a level of the clock signal CLK is fixed at H level and the charge pump circuit 51 is deactivated. When the boosted potential Vpp falls to be lower than the target potential Vt, the activating signal xcfx86EN goes to H level to again activate the charge pump circuit 51. Hence, the boosted potential Vpp is held at the target potential Vt.
There was a problem, however, since in a prior art boosted potential generating circuit, when, as shown in FIG. 14, the boosted potential Vpp reaches the target potential Vt in a period in which the clock signal CLK is at L level and the activating signal xcfx86EN is lowered from H level to L level, then the clock signal CLK is raised to H level in response to the falling edge of the activating signal xcfx86EN and thereby, there arises a so-called glitch G in the clock signal CLK. When such a glitch arises, the charge pump circuit 51 again supplies a positive electric charge in response to the rise of the clock signal CLK and the boosted potential Vpp rises excessively higher than the target potential Vt, even though the boosted potential Vpp has reached the target potential Vt.
It is accordingly a main object of the present invention is to provide a clock generating circuit capable of preventing generation of a glitch.
In a clock generating circuit relating to the present invention, included are: an oscillator generating a reference clock signal; a first latch circuit, provided between a first and second nodes, and operating in synchronism with the reference clock signal; a second latch circuit, provided between the second node and an output node, and operating in synchronism with a complementary signal of the reference clock signal; and a logic circuit, provided between the output node and the first node, and providing a complementary level of a level on the output node to the first node to generate a clock signal when an activating signal is at a first level, while transmitting a level on the output node to the first node to cease generation of the clock signal when the activating signal is at a second level. Hence, since the clock signal is generated by frequency dividing the reference clock signal with the two latch circuits and the logic circuit, generation of a glitch in the clock signal can be prevented from occurring.
It is preferable that a noise filter for eliminating noise from an output signal of the logic circuit to provide the output signal to the first node is further provided between the output node of the logic circuit and the first node. In this case, even when noise occurs in an output signal of the logic circuit, generation of a glitch in the clock signal can be prevented from occurring.
It is further preferable that the oscillator is activated in response to transition of the activation signal to the first level, while being deactivated in response to transition thereof to the second level. In this case, since when the reference clock signal is unnecessary, the oscillator is deactivated, power consumption can be reduced.
It is still further preferable that further provided is a delay circuit delaying the activating signal by a prescribed time to provide the activating signal to the oscillator. In this case, even when a glitch occurs in the reference clock signal, generation of a glitch in the clock signal can be prevented from occurring since a frequency dividing circuit constructed from the two latch circuits and the logic circuit has ceased a frequency dividing operation in advance.
In another clock generating circuit relating to the present invention, included are: a ring oscillator including an odd number of first inverters connected in a ring configuration, being activated to generate a clock signal when an activating signal is at a first level, while being deactivated to cease generation of the clock signal when the activating signal is at a second level; and a latch circuit, connected to an output node of the ring oscillator, and holding a level of an output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. Hence, since a level of the clock signal is held without any alteration therein in response to transition of the activating signal from the first level to the second level, there is no chance for a glitch to occur in the clock signal.
It is preferable that one first inverter of the odd number of first inverters is a clocked inverter that is activated when the activating signal is at the first level, while being deactivated when the activating signal is at the second level, and whose output node serves as the output node of the ring oscillator. In this case, the clock inverter is deactivated to hold a level of the clock signal at an output level of the clocked inverter, in response to transition of the activating signal from the first level to the second level.
It is further preferable that the ring oscillator further includes: a transfer gate inserted between an output node of one first inverter of the odd number of first inverters and an input node of the subsequent first inverter thereof, and being conductive when the activating signal is at the first level, while being nonconductive when the activating signal is at the second level, wherein the input node of the subsequent inverter serves as an output node of the ring oscillator. In this case, the transfer gate becomes nonconductive and a level of the clock signal is held at an input level of the subsequent inverter of the transfer gate in response to transition of the activating signal from the first level to the second level.
It is further preferable that a first inverter includes first and second transistors of respective different conductivity types connected in series between first and second power source potential lines; and at least one constant current source connected in series to the first and second transistors between the first and second power source potential lines. In this case, even when a power source potential is altered, not only a current driving ability of a first inverter but also a frequency of the clock signal are both prevented from varying.
It is further preferable that a latch circuit includes: a second inverter connected between the output node of the ring oscillator and the output node of the clock generating circuit; and a clocked inverter, in inverse parallel connection to the second inverter, being deactivated when the activating signal is at the first level, while being activated when the activating signal is at the second level. In this case, the latch circuit can be constructed with ease.
It is further preferable that at least three second inverters are provided and the at least three second inverters are connected in series between the output node of the ring oscillator and the output node of the clock generating circuit. In this case, a gain of a latch circuit can be high; therefore, an output level of the latch circuit can be quickly rendered definite even when the latch circuit enters a metastable state.
It is further preferable that further provided is a noise filter inserted between an output node of the second inverter and the output node of the clock generating circuit and for eliminating noise from an output signal of the second inverter. In this case, generation of a glitch in the clock signal can be prevented from occurring with more of certainty.
It is further preferable that the clock signal is used as a driving clock signal for the charge pump circuit. In this case, it is prevented from occurring that a glitch occurs in the clock signal and an electric charge is excessively supplied from the charge pump circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.